The present invention relates generally to an internal voltage step-down circuit and more particularly to an internal voltage step-down that may reduce an externally applied power source voltage to a predetermined internal voltage that may be provided to an internal circuit such as a semiconductor integrated circuit.
In order to increase the capacity of a semiconductor storage device and/or decrease manufacturing costs, device elements (such as transistors) are made smaller or further miniaturized. However, as transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), are made smaller, gate oxide films are reduced. Thus, the breakdown voltage of the gate oxide films are reduced and a power source voltage supplied to the semiconductor integrated circuit must be reduced. Therefore, an internal power source voltage step-down system is conventionally used to reduce an externally applied power source voltage to a predetermined internal source voltage. The internal source voltage is then supplied to internal circuits such as a semiconductor integrated circuit. Additionally, in order to reduce power consumption in a system, the externally applied power source can be reduced.
Referring now to FIG. 15, a circuit schematic diagram of a conventional internal voltage step-down circuit and an internal circuit is set forth.
In FIG. 15, a conventional internal voltage step-down circuit 10 receives an external power source voltage VDD and a reference voltage VREF and provides an internal voltage VINT to an internal circuit 1 through an internal power source line 13. Conventional internal voltage step-down circuit 10 includes a differential amplifier 11 and a driver p-channel MOSFET (hereinafter referred to as a PMOS transistor) 12. Differential amplifier 11 receives reference voltage VREF at an inverting input terminal (indicated with a minusxe2x88x92) and internal voltage VINT at a non-inverting input terminal (indicated with a plus +) and provides an output to a gate electrode of driver PMOS transistor 12. Driver PMOS transistor 12 has a source electrode connected to receive external power source voltage VDD and a drain connected to internal power source line 13. In this way, conventional internal voltage step-down circuit 10 provides internal voltage VINT at the drain of driver PMOS transistor 12. Internal voltage VINT is a stepped-down voltage from external power source voltage VDD.
One or plural internal circuits 1 which consume an operating current I are connected to the internal power source line 13 to receive internal voltage VINT as a power source. In this way, internal voltage VINT is obtained by dividing external power source VDD by an impedance between the source and the drain of driver PMOS transistor 12 and an internal impedance of internal circuit 1.
In conventional voltage step-down circuit 10, differential amplifier 11 compares internal voltage VINT on internal power source line 13 with reference voltage VREF. For example, when internal voltage VINT becomes lower than reference voltage VREF, an output voltage of differential amplifier 11 is reduced. Thus, driver PMOS transistor 12 becomes more conductive to increase a current from external power source voltage VDD. As a result, internal voltage VINT rises. On the other hand, when internal voltage VINT becomes higher than reference voltage VREF, an output voltage of differential amplifier 11 is increased. Thus, driver PMOS transistor 12 becomes less conductive to reduce a current from external power source voltage VDD. As a result, internal voltage VINT drops. Through this feedback operation, internal voltage VINT is controlled to be equal to reference voltage VREF.
When memory access is not conducted, internal circuit 1 can be in an inactive state (standby mode). In this case, internal current I is a minute current on the order of a device leakage current of devices in internal circuit 1. Thus, a current I0 output through driver transistor 12 is also a minute current on the order of the device leakage current of devices in internal circuit 1 and internal voltage VINT is controlled such that it is equal to reference voltage VREF. On the other hand, when an active signal (such as an active signal pulse) is input to internal circuit 1 and internal circuit 1 is active, and the switching of devices in internal circuit 1 causes a higher internal current I. With a higher internal current I, the internal voltage VINT can be reduced. However, through the feedback operation of conventional step-down circuit 10, the control gate terminal of driver PMOS transistor 12 is pulled lower and the impedance of driver PMOS transistor 12 lowers. In this way, current I0 flowing external power source voltage VDD to internal voltage VINT increases and internal voltage VINT is controlled to be equal to reference voltage VREF.
However, when the potential of external power source voltage VDD is reduced, for example to reduce overall system power consumption, a potential difference between external power source voltage VDD and internal voltage VINT becomes small. Thus, the potential difference across driver PMOS transistor 12 is decreased and it becomes difficult to provide sufficient current I0 to maintain internal voltage VINT to the same potential as to reference voltage VREF. For example, when internal voltage VINT is 1.5 V and external power source voltage VDD is 1.8 V or less, a potential different between external power source voltage VDD and internal voltage VINT is 0.3 V or less, thus the potential difference between the source and the drain of driver PMOS transistor 12 is 0.3 V or less. With such a small potential difference between the source and the drain, driver PMOS transistor 12 may not provide sufficient current I0 to maintain internal voltage VINT to the same potential as to reference voltage VREF.
In particular, when an active signal is input and internal circuit 1 is in an active state, internal current I can rapidly increase. In this case, conventional voltage step-down circuit 1 has a delayed response before a reduced internal voltage VINT is restored to the potential of internal reference voltage VREF. Alternatively, when internal circuit 1 is switched from an active (operating) state to a standby (non-operating) state, internal current I is reduced to the leakage current of devices in internal circuit 1, voltage conventional voltage step-down circuit 1 cannot respond quickly to reduce output current I0 and overshoot occurs in the potential of internal voltage VINT. Operation of internal circuit 1 can be affected by such a variation in an internal power source voltage such as internal voltage VINT.
In order to improve the current capability of driver PMOS transistor 12 in conventional voltage step-down circuit 10, channel width W can be increased. When channel width W of driver PMOS transistor 12 increases, an operating current of differential amplifier 11 can be increased to increase amplification sensitivity and/or drive current. In this way, a response speed of conventional voltage step-down circuit 10 is increased to suppress variations in internal voltage VINT providing an internal power source. However, such an approach increases power consumption and/or the chip area occupied by conventional voltage step-down circuit 10.
In a dynamic random access memory (DRAM), a large current amount is consumed over a short period of time during a sense operation. When a conventional internal power source voltage step-down circuit is used to convert an external power source voltage into a predetermined internal voltage to provide a power supply for sensing operations or the like in a DRAM, a technique has been employed in which a driver PMOS transistor is automatically turned on in response to a trigger signal in anticipation of the large current demand. For example, in Japanese Patent Application laid-open 11-086542 A (JP 11-086542 A), an auxiliary current is provided from the external power source voltage node to the internal voltage node by causing a driver PMOS transistor to be turned on for a predetermined period in response to a trigger signal in the case where a large current is consumed in a sense operation or the like.
According to the technique described in JP 11-086542 A, when the internal circuit consumes a large current, a delay in the response of a conventional internal power source voltage step-down circuit to provide current to the internal voltage supply node is compensated for by providing current from the external power source voltage node through an auxiliary driver PMOS transistor. In this way, a reduction (undershoot) in internal voltage VINT may be prevented.
In the technique described in JP 11-086542 A, the auxiliary driver PMOS transistor is turned on for a predetermined period from a time when an active signal for conducting the sense operation is provided to the internal circuit (DRAM or the like). Thus, a current is provided from the external power source voltage node. However, when the current in provided from the external power source voltage through driver PMOS transistor, internal voltage VINT may vary (rise in this case) which may effect circuit operations.
For example, in a configuration as illustrated in FIG. 15, the operating current I consumed in internal circuit 1 can vary during a period that an active signal pulse is provided to internal circuit 1. However, in the technique described above in JP 11-086542 A, a current provided from the external power source voltage node to the internal voltage supply node through a driver PMOS transistor for a predetermined period after the trigger signal is receive may be a constant current. Thus, it is difficult to match the current consumed by internal circuit 1 with the current provided by the extra driver PMOS transistor which may further contribute to variations of internal voltage VINT.
Generally, when internal circuit 1 switches to an active state, a time delay may occur before operating current I is drawn from internal voltage supply line 13. Thus, a consumption current on internal voltage supply line 13 may not change for the time delay from a time when an active signal pulse is provided. Thus, if the extra driver PMOS transistor as disclosed in JP 11-086542 A is turned on during this period to provide a current from an external power source, an excessive current may be provided and internal voltage VINT may increase.
Also, according to the technique described in JP 11-086542 A, at a time the extra PMOS transistor is turned off, internal circuit 1 is in an active state. Subsequently, when internal circuit 1 transitions from an active state to a standby state, current I may be greatly reduced. However, the conventional voltage step-down circuit may not be able to rapidly switch from providing a large current I0 to provide a small current I0. In this way, variations in internal voltage VINT may not be suppressed.
In view of the above discussion, it would be desirable to provide a means for suppressing a variation in an internal voltage which may be caused by a variation in current consumed by an internal circuit. It would also be desirable to suppress an internal voltage without providing an excessive current to an internal voltage supply line. It would also be desirable to suppress variations of an internal voltage when an internal circuit switches from an active state to a standby state which may cause a current consumed by the internal circuit to be greatly and rapidly reduced.
According to the present embodiments, a voltage step-down circuit that may provide an internal voltage by reducing an external power source is disclosed. A voltage step-down circuit may include a voltage step-down portion and a compensation current source portion. A voltage step-down portion may compare a reference voltage with an internal voltage and control an output current accordingly. An internal circuit connected to receive internal voltage may transition from a standby state to an active state in accordance with an activation signal. A compensation current source portion may provide a compensation current when internal circuit is in a standby state. In this way, voltage step-down portion may be biased to provide sufficient output current so that a response time may be improved and variations in internal voltage may be reduced.
According to one aspect of the embodiments, a voltage step-down circuit may include a voltage step-down portion and a compensation current portion. A voltage step-down portion may compare a reference voltage with an internal voltage and may generate the internal voltage by reducing an external power source voltage in accordance with a comparison result. An internal voltage supply line may receive the internal voltage and may provide power to an internal circuit. The internal circuit may have an active state and an inactive state. A compensation current source portion may be connected to the internal voltage supply line and may provide a compensation current for compensating an output current of the voltage step-down portion at a time when the internal circuit is in the inactive state.
According to another aspect of the embodiments, a voltage step-down circuit may include a voltage step-down portion. A voltage step-down portion may compare a reference voltage with an internal voltage and may generate the internal voltage by reducing an external power source voltage in accordance with a comparison result. An internal voltage supply line may receive the internal voltage and may provide power to an internal circuit. The internal circuit may have an active state and an inactive state. The voltage step-down portion may include a differential amplifier, an amplifier, and a driver transistor. The differential amplifier may be connected to receive the reference voltage at a first input terminal and the internal voltage at a second input terminal and may provide the comparison result. The amplifier may receive the comparison result and may provide an amplifier output. Power to the amplifier may be provided by the internal voltage supply line. The driver transistor may provide a current path for an output current between the external power source voltage and the internal voltage supply line and may have a driver transistor control terminal connected to receive the amplifier output. The amplifier may provide a compensation current for compensating the output current of the voltage step-down portion at a time when the internal circuit is in the inactive state.
According to another aspect of the embodiments, a voltage step-down circuit may include a voltage step-down portion. A voltage step-down portion may compare a reference voltage with an internal voltage and may generate the internal voltage by reducing an external power source voltage in accordance with a comparison result. An internal voltage supply line may receive the internal voltage and may provide power to an internal circuit. The internal circuit may have an active state and an inactive state. The voltage step-down portion may include a voltage dividing circuit, a differential amplifier, an amplifier, and a driver transistor. The voltage dividing circuit may provide a voltage dividing output by dividing the internal voltage. The differential amplifier may be connected to receive the reference voltage at a first input terminal and the voltage dividing output at a second input terminal and may provide the comparison result. The amplifier may receive the comparison result and may provide an amplifier output. Power to the amplifier may be provided by the internal voltage supply line. The driver transistor may provide a current path for an output current between the external power source voltage and the internal voltage supply line and may have a driver transistor control terminal connected to receive the amplifier output. The voltage dividing circuit, the differential amplifier, and the amplifier may provide a compensation current for compensating the output current of the voltage step-down portion at a time when the internal circuit is in the inactive state.
According to another aspect of the embodiments, a voltage step-down circuit may include a voltage step-down portion. A voltage step-down portion may compare a reference voltage with an internal voltage and may generate the internal voltage by reducing an external power source voltage in accordance with a comparison result. An internal voltage supply line may receive the internal voltage and may provide power to an internal circuit. The internal circuit may have an active state and an inactive state. A functional circuit may be connected to receive power from the internal voltage supply line and may provide a compensation current for compensating an output current of the voltage step-down portion at a time when the internal circuit is in the inactive state.
According to another aspect of the embodiments, a voltage step-down circuit may include a voltage step-down portion. A voltage step-down portion may compare a reference voltage with an internal voltage and may generate the internal voltage by reducing an external power source voltage in accordance with a comparison result. An internal voltage supply line may receive the internal voltage and may provide power to an internal circuit. The internal circuit may have an active state and an inactive state. A device parameter of the internal circuit may be set so that an internal circuit leakage current consumed from the internal voltage supply line may be at least a predetermined value at a time when the internal circuit is in the inactive state.
According to another aspect of the embodiments, the voltage step-down portion may include a differential amplifier and a driver transistor. The differential amplifier may receive the reference voltage at a first input terminal and the internal voltage at a second input terminal and may provide the comparison result. The driver transistor may provide a current path for the output current between the external power source voltage and the internal voltage supply line and may receive the comparison result at a driver transistor control terminal.
According to another aspect of the embodiments, the driver transistor may be a p-type insulated gate field effect transistor (IGFET). The driver transistor may have a driver transistor source connected to receive the external power source voltage and a driver transistor drain connected to the internal voltage supply line.
According to another aspect of the embodiments, the compensation current may be essentially disabled when the internal circuit is in the active state and a consumption current of the internal circuit is increased as compared to when the internal circuit is in the inactive state.
According to another aspect of the embodiments, the compensation current source portion may include a n-type IGFET and a bias voltage generating circuit. The n-type IGFET may provide a controllable current path between the internal voltage supply line and a ground potential. The bias voltage generating circuit may provide a bias voltage to a control gate of the n-type IGFET for setting the compensation current.
According to another aspect of the embodiments, the compensation current source portion may include a first n-type IGFET, a second n-type IGFET, and a bias voltage generating circuit. The first n-type IGFET may have a first controllable impedance path connected in series with a second controllable impedance path of a second n-type IGFET between the internal voltage supply line and a ground potential. A control gate of the first n-type IGFET may receive a control signal for inhibiting the compensation current when the internal circuit is in the active state and a consumption current of the internal circuit is increased as compared to when the internal circuit is in the inactive state. The bias voltage generating circuit may provide a bias voltage to a control gate of the second n-type IGFET for setting the compensation current.
According to another aspect of the embodiments, the compensation current source portion may include a first n-type IGFET and a second n-type IGFET. The first n-type IGFET may be connected in series with a first programmable device between the internal voltage supply line and a ground potential. The second n-type IGFET may be connected in series with a second programmable device between the internal voltage supply line and the ground potential.
According to another aspect of the embodiments, the compensation current source portion may include a first voltage dividing circuit, a first inverting amplifier, and a n-type IGFET. The first voltage dividing circuit may be connected between the internal voltage supply line and a ground potential and may provide a first voltage dividing output. The first inverting amplifier may receive the first voltage dividing output and may provide a first inverting amplifier output. The n-type IGFET may provide a controllable impedance path between the internal voltage supply line and the ground potential and may receive the first inverting amplifier output at a control gate.
According to another aspect of the embodiments, the first inverting amplifier may include a first n-type IGFET and a second n-type IGFET. The first n-type IGFET may have a source connected to the ground potential, a drain connected to the first inverting amplifier output, and a gate connected to receive the first voltage dividing output. The second n-type IGFET may have a source connected to the first inverting amplifier output and a drain and a gate connected to the internal voltage supply line.
According to another aspect of the embodiments, the first voltage dividing output is set to a potential close to a threshold voltage of a n-type IGFET.
According to another aspect of the embodiments, the compensation current source portion may include a second voltage dividing circuit, a second inverting amplifier, and a p-type IGFET. The second voltage dividing circuit may be connected between the internal voltage supply line and a ground potential and may provide a second voltage dividing output. The second inverting amplifier may receive the second voltage dividing output and may provide a second inverting amplifier output. The p-type IGFET may provide a controllable impedance path between the internal voltage supply line and the ground potential and may receive the second inverting amplifier output at a control gate.
According to another aspect of the embodiments, the first inverting amplifier may include a first p-type IGFET and a second p-type IGFET. The first p-type IGFET may have a source connected to the internal voltage supply line, a drain connected to the second inverting amplifier output, and a gate connected to receive the second voltage dividing output. The second p-type IGFET may have a source connected to the first inverting amplifier output and a drain and a gate connected to the ground potential.
According to another aspect of the embodiments, the second voltage dividing output is set to a potential close to a threshold voltage of a p-type IGFET below the internal voltage.
According to another aspect of the embodiments, the amplifier may include a p-type IGFET and a n-type IGFET. The p-type IGFET may have a source connected to the internal voltage supply line, a gate connected to receive the comparison result, and a drain connected to the amplifier output. The n-type IGFET may have a source connected to the ground potential and a drain connected to the amplifier output.
According to another aspect of the embodiments, the amplifier may include a p-type load IGFET and a n-type IGFET. The p-type load IGFET may have a source connected to the internal voltage supply line and a drain connected to the amplifier output. The n-type IGFET may have a source connected to the ground potential, a drain connected to the amplifier output, and a gate connected to receive the comparison result.